The desire for higher packing densities, faster circuit speed, and lower power dissipation has driven the scaling of semiconductor devices to smaller dimensions. As these devices, such as, for example, metal-oxide-semiconductor field effect transistors (MOSFETs) become smaller, different materials are required to perform the needed functions. This has led to low-k dielectric materials and high conductivity metals being used in the devices.
Many current low-k dielectrics and next generation ultra-low dielectric constant (ULK) dielectrics, however, typically are porous. This porosity often leads to exposed pores and surface roughness in, and on, trench and via surfaces and sidewalls. Additionally, formation of trench and via structures can expose and open pores and form defects such as excessive side-wall roughness or micro-trenching at the surface, trench/via bottom, and on trench/via sidewalls of the dielectric. Exposed pores and defects can provide entry points for intercalation and diffusion into the dielectric of unwanted species from the fabrication environment or processing. These unwanted species can serve to compromise the chemical, structural, and/or electrical integrity of the dielectric, raise the effective dielectric constant of the dielectric, increase leakage currents, limit device lifetime and reliability, and/or interact detrimentally with downstream fabrication chemistries. Further, as a result of surface roughness and open porosity, it is difficult for subsequent thin films to smoothly cover and deposit, defect free, on the low-k dielectric film.
Copper diffusion barriers are often deposited on low-k dielectrics to prevent copper from diffusing into the low-k dielectric. Copper diffusion barriers, however, must be very thin while still maintaining good integrity in order to function properly. When deposited over rough or porous surfaces, the copper diffusion barrier often is deposited with defects, such as “pin-holes”, cracks, breaks, thin-spots, or incomplete coverage which compromise the integrity and functionality of the barrier layer. Moreover, low-k dielectrics that have exposed pores or the like are susceptible to diffusion of the barrier precursor materials into the internal matrix of the porous low-k dielectric. This can lead to an increase in leakage current and a decrease in reliability lifetime of the device.
A conventional method and device are shown in FIGS. 1A-1D. As shown in FIG. 1A, a porous low-k dielectric material 20 is formed on a substrate 10. A recess 30 with sidewalls 32 is patterned and formed in low-k dielectric material 20 so as to expose a portion of substrate 10 at a bottom 34 of recess 30. However, pores and defects 50a form in and on the surface of the low-k dielectric 20 during fabrication as a result of the inherent porosity and roughness of the dielectric, and also as a result of subsequent etching of the low-k dielectric material 20. As shown in FIG. 1B, after forming recess 30 a copper diffusion barrier 40 is typically deposited over low-k dielectric material 20 and in recess 30 so as to cover the exposed substrate 10 at bottom 34 and sidewalls 32. As can be seen in FIG. 1B, defects 50b typically form in the copper diffusion barrier 40 as a result of the high porosity, roughness, and defects 50a of the low-k dielectric material 20.
Previous attempts to improve devices have included a plasma treatment 35 of the porous low-k dielectric material 20, as shown in FIG. 1C. The plasma treatment, however, has had limited success. For example, prior plasma treatments directly to porous low-k dielectric materials, and especially to porous ULK layers, can lead to densification or damage layers that extend tens to hundreds of nanometers into the dielectric layer. Densification leads to increased k-value due to the reduction of porosity. “Damage,” as used herein, refers to the depletion of carbon and/or other elements that originally served to lower the dielectric constant. “Damage” can also refer to the increase of silanol (Si—OH) bonds that drive increases in the dielectric constant. Generally, “damaged” dielectrics have an increased k-value. Typically, lower k dielectric materials and porous dielectric materials are more susceptible to plasma damage than are dielectrics with less porosity and/or higher k values. The net result has been that while successful pore sealing through plasma treatments has been demonstrated, it has come at a cost of increased k-values. As such, the benefit of using low-k materials, and thus practical implementation of this solution, has not been achieved.
Another attempted solution, as shown in FIG. 1D, has been to try to seal the pores using a trench/via liner, also called a pore-sealing liner, 60. Typical materials used for liner 60 have a dielectric constant between 2.9 and 6.8. An example of a conventional liner material is silicon nitride. When pore-sealing liners have been used in the past, however, pores and defects 50a in low-k dielectric material 20 cause trench liner 60 to also have defects, as shown in FIG. 1D with label 50c. Defects 50c in trench liner 60 correspond to defects or pores 50a in material 20. Further, barrier layer 40 formed over trench liner 60 also has defects 50b that correspond to the defects 50c in trench liner 60 and pores and defects 50a in porous low-k dielectric material 20. To overcome this, thicker trench liners have been used to fill in the pores and eliminate defects. However, typical trench liner materials negatively impact interconnect performance because by nature, they have a higher k-value than the low-k dielectric 20. Unfortunately, using thicker liners only increases the negative impact of the higher-k material. As a result, the use of trench liner 60 as a pore-sealing material has been impractical.
Attempts have also been made to use low-k dielectric materials as a trench liner as well. However, these materials by nature are porous and thus add additional defects to the system.
Thus, there is a need to overcome these and other problems of the prior art and to provide semiconductor devices with improved porous low-k dielectric layers.